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8 - channel das with 14 - bit, bipolar input, simultaneous sampling adc data sheet AD7607 rev. b information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. speci fications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2010 - 2012 analog devices, inc. all rights reserved. features 8 simultaneously sampled inputs true bipolar analog i nput ranges: 10 v, 5 v single 5 v analog supply and 2.3 v to 5 .25 v v drive fully integrated data acquisition solution analog input clamp p rotection input buffer with 1 m ? analog input i mpedanc e second - order antialiasing analog filter on - chip accurate reference and reference buffer 14- bit adc with 200 k sps on all channels flexible p arallel /s erial interface spi/qspi? / microwire? /dsp compatible pin - compatible so lutions from 14 bits to 18 bits perfo rmance 7 kv esd rating on a nalog input channels fast throughput rate: 200 ksps for all channels 85.5 db snr at 5 0 ksps inl 0.25 lsb, dnl 0.25 lsb low power: 100 mw at 200 ksps standby mode : 25 m w typical 64- lead lqfp package applications power - line moni toring and protection systems multiphase motor control instrumentation and control systems multi axis positioning systems data acquisition systems (das) table 1 . high resolution, bipolar input, simultaneous sampling das solutions res olution single - ended inputs number of simultaneous sampling channels 18 bits ad7608 8 16 bits ad7606 8 ad7606 -6 6 ad7606 -4 4 14 bits AD7607 8 functional block dia gram v1 v1gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v2 v2gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v3 v3gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v4 v4gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v5 v5gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v6 v6gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v7 v7gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h v8 v8gnd r fb 1m? 1m? r fb clamp clamp second- order lpf t/h 8:1 mux agnd busy frstdata convst a convst b reset range control inputs clk osc refin/refout ref select agnd os 2 os 1 os 0 d out a d out b rd/sclk cs par/ser/byte sel v drive 14-bit sar digital filter parallel/ serial interface 2.5v ref refcapb refcapa serial parallel regcap 2.5v ldo regcap 2.5v ldo av cc av cc db[15:0] AD7607 08096-001 figure 1. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 2 of 32 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 r evision history ............................................................................... 2 general description ......................................................................... 3 specifications ..................................................................................... 4 timing specifications .................................................................. 6 absolute maximum ratings .......................................................... 10 thermal resistance .................................................................... 10 esd caution ................................................................................ 10 pin configuration and function descriptions ........................... 11 typical performance characteristics ........................................... 14 terminology .................................................................................... 18 theory of operation ...................................................................... 19 converter details ........................................................................ 19 analog input ............................................................................... 19 adc transfer function ............................................................. 20 internal/external reference ...................................................... 21 typical connection diagram ................................................... 22 power - down modes .................................................................. 22 conversion control ................................................................... 23 digital interface .............................................................................. 24 parallel interface ( pa r /ser/byte sel = 0) .......................... 24 parallel byte interface ( pa r /ser/byte sel = 1, db15 = 1) .. 24 serial interface ( pa r /ser/byte sel = 1) ............................. 24 reading during conversion ..................................................... 25 digital filter ................................................................................ 26 layout guidelines ........................................................................... 29 outline dimensions ....................................................................... 31 ordering guide .......................................................................... 31 revision history 1/12 rev. a to rev. b changes to analog input range s section .................................... 19 7/10 re v. 0 to rev. a change to table 1 .............................................................................. 1 7 /10 revision 0 : initial versi on www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 3 of 32 general description the ad760 7 1 is a 14 - bit, simultaneous sampling , analog - to - digital data acquisition system (das). the part contains analog input clamp protection; a second - order antialiasing f ilter ; a track - and - hold amplifier; a 14 - bit charge redistribution, successive approximation analog - to - digital converter (adc); a flexible digital filter; a 2.5 v reference and reference buffer; and high speed serial and parallel interfaces. the AD7607 oper ates from a single 5 v supply and can accom - modate 10 v and 5 v true bipolar input signals while sampling at throughput rates of up to 200 ksps for all channels. the input clamp protection circuitry can tolerate voltages of up to 16.5 v. the AD7607 has 1 m? analog input impedance, regardless of sampling frequency. the single supply operation, on - chip filtering, and high input impedance eliminate the need for driver op amps and external bipolar supplies. the AD7607 antialiasing filter has a 3 db cutoff fr equency of 22 khz and provides 40 db antialias rejection when sampling at 200 ksps. the flexible digital filter is pin driven and can be used to simplify external filtering . 1 patent pending. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 4 of 32 specifications v ref = 2.5 v ex ternal/internal, av cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v, f sample = 200 ksps, t a = t min to t max , unless otherwise noted. 1 table 2 . parameter test conditions/comments min typ max unit dynamic performance f in = 1 khz sin e wave , unless otherwise noted signal -to -( noise + distortion ) (sinad) 2 , 3 no oversampling; 10 v range 84 84.5 db no oversampling; 5 v range 83.5 84.5 db signal -to - noise ratio (snr) 2 oversampling by 4, f in = 130 h z 85.5 db no oversampling 84.5 db total harmonic distortion (thd) 2 ? 107 ? 95 db peak harmonic or spurious noise (sfdr) 2 ? 108 db intermodulation distortion (imd) 2 fa = 1 khz, fb = 1.1 khz second - order terms ? 110 db third - order terms ? 106 db ch annel - to - channel isolation 2 f in on unselected channels up to 160 khz ? 95 db analog input filter full power bandwidth ? 3 db , 10 v range 23 k hz ? 3 db, 5 v range 15 k hz ? 0.1 db , 10 v range 10 k hz ? 0.1 db , 5 v range 5 k hz t group delay 10 v range 11 s 5 v range 15 s dc accuracy resolution no missing c odes 14 bits differential nonlinearity 2 0.25 0.95 lsb 4 integral nonlinearity 2 0.25 0.5 lsb positive /negative full - scale error 2 , 5 external reference 2 9 lsb internal reference 2 lsb positive full - scale error drift 2 external reference 2 ppm /c internal reference 7 ppm/c negative full - scale error drift external reference 4 ppm/c internal reference 8 ppm/c positive /negative f ull - scale error matching 2 10 v range 2 8 lsb 5 v range 4 10 lsb bipolar zero code error 2 , 6 10 v range 0.5 2 lsb 5 v range 1 3.5 lsb bipolar zero code error drift 2 10 v range 10 v/c 5 v range 5 v/c bipolar zero code error matching 10 v range 1 2.5 lsb 5 v range 3 6 lsb total unadjusted error (tue) 10 v range 0.5 lsb 5 v range 1 lsb analog input input voltage ranges range = 1 10 v range = 0 5 v input current + 10 v 5.4 a + 5 v 2.5 a input capaci tance 7 5 pf input impedance see the analog input section 1 m www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 5 of 32 parameter test conditions/comments min typ max unit reference input/output reference input voltage range 2.475 2.5 2.525 v dc leakage current 1 a input capacitance 7 ref select = 1 7.5 pf reference output voltage refin/refout 2.49/ 2.505 v reference temperature coefficient 10 ppm/c logic inputs input high voltage (v inh ) 0.9 v drive v input low voltage (v inl ) 0.1 v drive v input current (i in ) 2 a input capacitance (c in ) 7 5 pf logic outputs output high voltage (v oh ) i source = 1 00 a v drive ? 0.2 v output low voltage (v ol ) i sink = 1 00 a 0.2 v floating - state leakage current 1 20 a floating - state output capacitance 7 5 pf output coding twos complement conversion rate conv ersion time all eight channels included; see table 3 4 s track - and - hold acquisition time 1 s throughput rate a ll eight channels included 200 ksps power requirements av cc 4.75 5.25 v v drive 2.3 5.25 v i to tal digital inputs = 0 v or v drive normal mode (static) 16 22 ma normal mode (operational) 8 20 27 ma standby mode 5 8 ma shutdown mode 2 6 a power dissipation 8 normal mode (static) 80 115.5 mw normal mode (operational) 100 142 mw standby mode 25 42 mw shutdown mode 10 31.5 w 1 temperature range for the b version is ?40c to +85c. 2 see the terminology section. 3 this specification applies when reading during a conversion or after a conversion. if reading during a conversion in parallel mode with v drive = 5 v, snr typically reduces by 1.5 db and thd typically reduces by 3 db . 4 lsb means least significant bit. with 5 v input range, 1 lsb = 610.35 v. with 10 v input range, 1 lsb = 1.22 mv. 5 this specification includes the full temperature range variation and contribution from the internal reference buffer but do es not include the error contribution from the external reference. 6 bipolar zero code error is cal culated with respect to the analog input voltage. 7 sample tested during initial release to ensure compliance. 8 operational power/current figure includes contribution when running in oversampling mode. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 6 of 32 timing specification s av cc = 4.75 v to 5.25 v, v drive = 2.3 v to 5.25 v, v ref = 2.5 v external reference/ internal reference, t a = t min to t max , unless otherwise noted. 1 table 3 . limit at t min , t max parameter min typ max unit description parallel /serial/byte mode t cycle 1/throughput rate 5 s parallel mode, reading during or af ter conversion; or serial mode ( v dri ve = 3.3 v to 5.25 v ) , reading during a conversion using d out a and d out b lines 5 s serial mode reading during conversion ; v drive = 2.7 v 9.1 s serial m ode reading after a conversion; v drive = 2.3 v, d out a and d out b lines t conv conversion tim e 3.45 4 4.15 s oversampling off 7 .87 9 .1 s oversampling by 2 16 .05 18.8 s oversampling by 4 3 3 39 s oversampling by 8 66 78 s oversampling by 1 6 133 158 s oversampling by 32 257 315 s oversampling by 64 t wake - up standby 100 s stby rising edge to convst x rising edge ; power - up time from standby mode t wake - up shutdown internal reference 30 ms stby rising edge to convst x rising edge ; power - up time from shutdown mode external referen ce 13 ms stby rising edge to convst x rising edge ; power - up time from shutdown mode t reset 50 ns reset high pulse width t os_ setup 20 ns busy to os x pin setup time t os_hold 20 ns busy to os x pin hold time t 1 40 ns convst x high to busy high t 2 25 ns minimum convst x low pulse t 3 25 ns minimum convst x high pulse t 4 0 ns busy falling edge to cs falling edge setup time t 5 2 0.5 ms maximum delay allowed between convst a, convst b rising edges t 6 25 ns maximum time between last cs rising edge and busy falling edge t 7 2 5 ns minimum delay between reset low to convst x high parallel/byte read operation t 8 0 ns cs to rd setup time t 9 0 ns cs to rd hold time t 10 rd low pulse width 16 ns v drive above 4.75 v 21 ns v drive above 3.3 v 25 ns v drive above 2.7 v 32 ns v drive above 2.3 v t 11 15 ns r d high pulse width t 12 22 ns cs high pulse width (see figure 5 ); cs and rd linked www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 7 of 32 limit at t min , t max parameter min typ max unit description t 13 delay from cs until db[15:0] three - state disabled 16 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v t 14 3 data access time after rd falling edge 16 ns v drive above 4.75 v 21 ns v drive above 3.3 v 25 ns v drive above 2.7 v 32 ns v drive above 2.3 v t 15 6 ns data hold time after rd falling edge t 16 6 ns cs to db[15:0] hold time t 17 22 ns delay from cs ri sing edge to db[15:0] three - state enabled serial read operation f sclk frequency of serial read clock 23.5 mhz v drive above 4.75 v 17 mhz v drive above 3.3 v 14.5 mhz v drive above 2.7 v 11.5 mhz v drive above 2.3 v t 18 delay f rom cs until d out a/d out b three - state disabled/d elay from cs until msb valid 15 ns v drive above 4.75 v 20 ns v drive above 3.3 v 30 ns v drive = 2.3 v to 2.7 v t 19 3 data access time after sclk rising edg e 17 ns v drive above 4.75 v 23 ns v drive above 3.3 v 27 ns v drive above 2.7 v 34 ns v drive above 2.3 v t 20 0.4 t sclk ns sclk low pulse width t 21 0.4 t sclk ns sclk high pulse width t 22 7 sclk rising edge to d out a/d out b valid hol d time t 23 22 ns cs rising edge to d out a/d out b three - state enabled frstdata operation t 24 delay from cs falling edge until frstdata three - state disabled 15 ns v drive above 4.75 v 20 ns v drive abov e 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v t 25 ns delay from cs falling edge until frstdata high, serial mode 15 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v d rive above 2.3 v t 26 delay from rd falling edge to frstdata high 16 ns v drive above 4.75 v 20 ns v drive above 3.3 v 25 ns v drive above 2.7 v 30 ns v drive above 2.3 v www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 8 of 32 limit at t min , t max parameter min typ max unit description t 27 delay from rd falling e dge to frstdata low 19 ns v drive = 3.3 v to 5.25 v 24 ns v drive = 2.3 v to 2.7 v t 28 delay from 16 th sclk falling edge to frstdata low 17 ns v drive = 3.3 v to 5.25 v 22 ns v drive = 2.3 v to 2.7 v t 29 24 ns delay from cs rising edge until frstdata three - state enabled 1 sample tested during initial release to ensure co mpliance. all input signals are specified with t r = t f = 5 ns (10% to 90% of v drive ) and timed from a voltage level of 1.6 v. 2 the delay between the convst x signals was measured as the maximum time allowed while ensuring a <3 lsb performance matching between channel sets. 3 a buffer, which is equivalent to a load of 20 pf on the output pins, i s used on the data o utput pins for t hese measurements. timing diagrams t cycle t 3 t 5 t 2 t 4 t 1 t 7 t reset t conv convst a, convst b convst a, convst b busy cs reset 08096-002 figure 2. convst t iming reading after a c onversion t cycle t 3 t 5 t 6 t 2 t 1 t conv convst a, convst b convst a, convst b busy cs t 7 t reset reset 08096-003 figure 3. convst timing reading during a c onversion data: db[15:0] frstdata cs rd in v alid v1 v2 v3 v7 v8 v4 t 10 t 8 t 13 t 24 t 26 t 27 t 14 t 11 t 15 t 9 t 16 t 17 t 29 08096-004 figure 4. parallel mode , separate cs and rd p ulses www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 9 of 32 08096-005 data: db[15:0] frstdata cs and rd v1 v2 v3 v4 v5 v6 v7 v8 t 12 t 13 t 16 t 17 figure 5. linked parallel mode, cs and rd sclk d out a, d out b frstdata cs db13 db12 db11 db1 db0 t 18 t 19 t 21 t 20 t 23 t 29 t 28 t 25 08096-006 t 22 figure 6. serial read operatio n (channel 1) 08096-007 data: db[7:0] frstdata cs rd invalid high byte v1 low byte v1 high byte v8 low byte v8 t 8 t 13 t 14 t 24 t 26 t 27 t 11 t 17 t 29 t 16 t 9 t 15 t 10 figure 7. byte mode read o peration www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 10 of 32 absolute maximum rat ings t a = 25c, unless otherwise noted . table 4 . parameter rating a v cc to agnd ? 0.3 v to + 7 v v drive to a gnd ? 0.3 v to a v cc + 0.3 v analog input voltage to agnd 1 16.5 v digital input voltage to a gnd ? 0.3 v to v drive + 0.3 v digital output voltage to a gnd ? 0.3 v to v drive + 0.3 v refin to agnd ? 0.3 v to av cc + 0.3 v input curre nt to any pin except supplies 1 10 ma operating temperature range b version ? 40c to +85c storage temperature range ? 65c to +150c junction temperature 150c pb/sn temperature, soldering reflow (10 sec to 30 sec) 240 (+ 0)c pb - free temperature, soldering reflow 260 (+ 0)c esd (all pins e xcept analog inputs) 2 kv esd (analog input pins o nly) 7 kv 1 transient currents of up to 100 ma do not cause scr latch - up. stresses above those listed under absolute maximum ratings may cause permanent dama ge to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for ex tended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. these specifications apply to a 4 - layer board. table 5 . thermal resistance package type ja jc unit 64- lead lqfp 45 11 c /w esd caution www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 11 of 32 pin configuration an d function descripti ons AD7607 top view (not to scale) 64 63 62 61 60 59 58 57 v1gnd 56 55 54 53 52 51 50 49 v5 v4 v6 v3 v2 v1 pin 1 v7 v8 v2gnd v3gnd v4gnd v5gnd v6gnd v7gnd v8gnd db13 db12 db11 db14/hben v drive db1 17 18 19 20 21 22 23 24 25 agnd 26 27 28 29 30 31 32 db2 db3 db4 db5 db6 db7/d out a db9 db10 db8/d out b agnd av cc 1 3 4 frstdata 7 6 5 os 2 2 8 9 10 12 13 14 15 16 11 db0 busy convst b convst a range reset rd/sclk cs par/ser/byte sel os 1 os 0 stby decoupling cap pin data output power supply analog input ground pin digital output digital input reference input/output db15/byte sel refin/refout 48 46 45 42 43 44 47 41 40 39 37 36 35 34 33 38 agnd av cc refgnd refcapa agnd agnd agnd refcapb refgnd regcap regcap av cc av cc ref select 08096-008 figure 8 . pin configuration table 6 . pin function desc riptions pin no. type 1 mnemonic description 1, 37, 38, 48 p av cc analog supply voltage, 4.75 v to 5.25 v. this supply voltage i s applied to the internal front - end amplifiers and to the adc core. these supply pins should be decoupled to agnd . 2, 26, 35, 40, 41, 47 p agnd analog ground. these pins are the g round reference point s for all analog circuitry on the AD7607 . all analog input signals and external reference signal s should be referred to th e s e pin s. all six of the se agnd pins should connect to the a gnd plane of a system. 5, 4, 3 di os[2:0] oversampling mode pins. logic inputs. these inputs are used to select the oversampling ratio. os 2 is the msb control bit, and os 0 is the lsb control bit. see the digital filter section for more details about the oversampling mode of operation and table 9 for oversampling bit decoding. 6 di par /ser/ byte sel parallel/serial/byte interface selection i nput. logic input. if this pin is tied to a logic low, the parallel interface is selected . if this pin is tied to a logic high , the serial interface is selected. parallel byte interface mode is selected when this pin is logic high and db15/byte sel is logic high (s ee table 8 ). in serial mode, the rd /sclk pin function s as the serial clock input. the db7/d out a pin and t he db8/d out b pin function as serial data output s . when the serial interface is selected, the db[15:9] and db[6 :0] pins should be tied to ground . in byte mode, db15, in conjunction with par /ser/byte sel, is used to select the parallel byte mode of operation (see table 8 ). db14 is used as the hben pin. db[7 :0] transfer the 16 - bit conversion results in two rd operations, with db0 as the lsb of the data transfers. 7 di stby standby mode input. this pin is used to place the AD7607 into one of two power - down modes: standby mo de or shutdown mode. the power - down mode entered depends on the state of the range pin, as shown in table 7 . when in standby mode, all circuitry, except the on - chip reference, regulators, and regulator buffers, is powered down. when in shutdown mode, all circuitry is powered down . 8 di range analog i nput range s elec tion . logic input. the polarity on this pin determines the input range of the analog input channels. if this pin is tied to a logic high, the analog inp ut range is 10 v for all channels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin has an immediate effect on the analog input range. changing this pin during a conversion is not recommended. see the analog input section for more information. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 12 of 32 pin no. type 1 mnemonic description 9, 10 di convst a, convst b conversion start input a, conversion start input b. logic inputs. these logic inputs are used to initiate conversions on the analog i nput channels . for simultaneous sampling of all 8 input channels convst a and convst b can be shorted together and a single convert start signal applied. alternatively, convst a can be used to initiate simultaneous sampling for v1, v2, v3, and v4; and conv st b can be used to initiate simultaneous sampling on the other analog inputs (v5, v6, v7, and v 8). this is possible only when oversampling is not switched on. when the convst a or convst b pin transitions from low to high, the front - end track - and - hold cir cuitry for their respective analog inputs is set to hold. 11 di reset reset input. when set to logic high, the rising edge of reset resets the AD7607 . the part shoul d receive a reset pulse after power - up. the reset high pulse should typically be 50 ns wi de. if a reset pulse is applied during a conversion, the conversion is aborted. if a reset pulse is applied during a read, the contents of the output registers reset to all zeros. 12 di rd /sclk pa rallel data read control input w hen the p arallel interface is selected ( rd )/ serial clock input w hen the serial interface is s elected (sclk) . when both cs and rd are logic low in parallel mo de, the output bus is enabled. in serial mode , this pi n acts as the serial c lock input for data transfers. the cs falling edge takes the d out a and d out b data output l ines out of tri state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent dat a bits onto the d out a and d out b serial data outputs . for more information, see the conversion control section. 13 di cs chip select. this active low logic input frames the data transfer. when both cs and rd are logic low in parallel mode, the db[15:0] output bus is enabled and the conversion result is output on the parallel data bus lines. in serial mode, cs is used to frame the serial read transfer and clock out th e msb of the serial output data. 14 do busy busy output. this pin transitions to a logic high after both convst a and convst b rising edges and indicates that the conversion process has started. the busy output remains high until the conversion process fo r all channels is complete. the falling edge of busy signals that the conversion data is being latched into the output data registers and is available to read after a time t 4 . a ny data read while busy is high must be completed before the falling edge of bu sy occurs. rising edges on convst a or convst b have no effect while the busy signal is high. 15 d o frstdata digital output. the frstdata output signal indicates when the first channel, v1, is being re ad back on the parallel, parallel byte, or serial inte rface. when the cs input is high , the frstdata output pin is in three - state. the falling edge of cs takes frstdata out of three - state. in parallel mode , the falling edge of rd corresp onding to the resul t of v1 then set s the frstdata pin high, which indicates that the result from v1 is available on the output data bus. the frstdata output returns to a logic low following the next falling edge of rd . in serial mode, frstdata goes high on the falling edge of cs because this cloc ks out the msb of v1 on d out a. it returns low on the 1 4 th sclk falling edge after the cs falling edge. see the conversion control section for more details. 22 to 16 do db[6:0] parallel output data bits, db6 to db0. when par /ser /byte sel = 0, these pins act as three - state parallel digital input/output pins. when cs and rd are low, t hese pins are used to output db6 to db0 of the conversion result. when par /ser /byte sel = 1, these pins should be tied to dgnd . when operating in parallel byte interf ace mode, db[7:0] outputs the 14 - bit conversion result in two rd operations. db7 is the msb, and db0 is the lsb . 23 p v drive logic power supply input. the voltage ( 2.3 v to 5 .25 v) supplied at this pin determines the operating voltage of the interfa ce. this pin is nominally at the same supply as the supply of the host interface (that is, dsp and fpga). 24 do db7/d out a parallel output data bit 7 (db7)/serial interface data output pin (d out a). when par /ser /byte sel = 0, this pins acts as a three - state parallel digital input/ output pin. when cs and rd are low, this p in is used to output db7 of the conversion result. when par /ser /byte sel = 1, this pin functions as d out a and outputs serial conversion data (see the convers ion control section for more details). when operating in parallel byte mode, db7 is the msb of the byte. 25 do db8/d out b parallel output data bit 8 (db8)/serial interface data output pin (d out b). when par /ser /byte sel = 0, this pin act s as a three - state parallel digital input/output pin. when cs and rd are low, this p in is used to output db8 of the conversion result. when par / ser /byte sel = 1, this pin functions as d out b and outputs serial conversion data (see the conversion control section for more details). 31 to 27 do db [13:9] parallel output data bits, db13 to db9. when par /ser /byte sel = 0, these pins act as three - stat e parallel digital input/output pins. when cs and rd are low, these pins are used to output db13 to db9 of the conversion result. when par /ser /byte sel = 1, these pins should be tied to dgnd . www.datasheet.co.kr datasheet pdf - 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data sheet AD7607 rev. b | page 13 of 32 pin no. type 1 mnemonic description 32 do/di db14/hben parallel output data bit 14 (db14)/high byte enable (hben). when par /ser /byte sel = 0, this pin act s as a three - state parallel digital output pin. when cs and rd are low, this pin is used to o utput db14 of the conversion result , which is a sign extended bit of the msb , db13 . when par /ser /byte sel = 1 and db15/byte sel = 1, the AD7607 operate s in parallel byte interface mode , in which the hben pin is used to select if the most significant byte (msb) or the least significant byte (lsb) of the conversion result is output first. when hben = 1, the msb byte is out put first, followed by the lsb byte . when hben = 0, the lsb byte is output first, followed by the msb byte . 33 do/di db1 5/ byte sel parallel output data bit 15 (db15)/paralle l byte mode select (byte sel). when par /ser /byte sel = 0, this pin acts as a three - state parallel digital output pin. when cs and rd are low, this p in is used to output db15 , which is a sign extended bit of the msb , db13 , of the conversion result. when par / ser /byte sel = 1, the byte sel pin is used to select between serial interface mode or parallel byte interface mode (see table 8 ). when par /ser /byte sel = 1 and db15/byte sel = 0, the AD7607 operates in serial interface mode. when par /ser /byte sel = 1 and db15/byte sel = 1, the AD7607 operates in parallel byte interface m ode. 34 di ref select internal/external reference selection input. logic input. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the refin/refout pin. 36, 39 p regcap decoupling capacitor pin for voltage output from internal regulator. these output pin s should be decoupled separately to agnd using a 1 f capacitor. the voltage on the s e pin s is in the ran ge of 2.5 v to 2.7 v. 42 ref refin/ refout reference input (refin) /reference output (refout) . the gained up on - chip reference of 2.5 v is available on this pin for external use if the ref select pin is set to a logic high. alternatively, the inter nal refe rence can be disabled by setting the ref select pin to a logic low , and an external reference of 2.5 v can be applied to this input (see the internal/external reference section ) . decoupling is required on this pin for both the int ernal or ex ternal reference options. a 10 f capacitor should be applied from this pin to ground close to the refgnd pins. 43, 46 ref refgnd reference ground pins. these pins should be connected to agnd. 44, 45 ref refcapa, refcapb reference buffer outpu t force/sense pins. these pins must be connected together and decoupled to agnd using a low esr 10 f ceramic capacitor. 49 , 51, 53, 55, 57, 59, 61, 63 ai v1 to v8 analog input s . the s e pin s are single - ended analog input s . t he analog input range o f the s e channel s is determined by the range pin . 50, 52 , 54, 56, 58, 60, 62, 64 ai gnd v1gnd to v8 gnd analo g input ground pins. these pins corre spond to analog input pin v1 to analog input pin v8 . all analog input agnd pins should connect to the agnd plane of a system. 1 p = power supply, di = digital input, do = digital output, ref = reference input/output, ai = analog input, gnd = ground. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 14 of 32 typical performance characteristics 08096-018 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 90 100 snr (db) input frequenc y (khz) av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 10v range snr: 85.07db thd: ?107.33db 16,384 point fft f in = 1khz figure 9 . fft 10 v range 08096-017 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 10 20 30 40 50 60 70 80 90 100 snr (db) input fequenc y (khz) av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 5v range snr: 84.82db thd: ?107.51db 16,384 point fft f in = 1khz figure 10 . fft plot 5 v range ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 in l (lsb) code av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 10v range 08096-019 figure 11 . typical inl 10 v range ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 dn l (lsb) code av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 10v range 08096-020 figure 12 . typical dnl 10 v range ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0 2000 4000 6000 8000 10,000 12,000 14,000 16,000 in l (lsb) code av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 5v range 08096-010 figure 13 . typical inl 5 v ran ge ? 0.5 ? 0.4 ? 0.3 ? 0.2 ? 0.1 0 0.1 0.2 0.3 0.4 0.5 dn l (lsb) code av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 5v range 0 2000 08096-009 4000 6000 8000 10,000 12,000 14,000 16,000 figure 14 . typical dnl 5 v range www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 15 of 32 5.00 3.75 2.50 1.25 0 ?1.25 ?2.50 ?3.75 ?40 ?25 ?10 5 20 35 50 65 80 ?5.00 nfs error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08096- 1 15 figure 15 . nfs error vs. temperature 5.00 3.75 2.50 1.25 0 ?1.25 ?2.50 ?3.75 ?40 ?25 ?10 5 20 35 50 65 80 ?5.00 pfs error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08096- 1 16 figure 16 . pfs error vs. temperature 2.5 ?40 ?25 ?10 5 20 35 50 65 80 ?2.5 ?2.0 ?1.5 ?1.0 ?0.5 0 0.5 1.0 1.5 2.0 nfs/pfs channel matching (lsb) temperature (c) 10v range av cc , v drive = 5v external reference pfs error nfs error 08096- 1 17 figure 17 . pfs and nfs erro r matching vs. temperature 10 8 6 4 2 0 0 120k 100k 80k 60k 40k 20k ?2 pfs/nfs error (%fs) source resistance (?) av cc , v drive = 5v f sample = 200 ksps t a = 25c external reference source resistance is matched on the vxgnd input 10v and 5v range 08096- 1 18 figure 18 . pfs and nfs error vs. source resistance 08096-022 80 81 82 83 84 85 86 10 100 1k 10k 100k snr (db) input frequenc y (hz) av cc = v drive = 5v internal reference f sample = 200ksps t a = 25c 5v range all 8 channels figure 19 . snr vs. input frequency 5 v range 80 81 82 83 84 85 86 10 100 1k 10k 100k snr (db) input frequenc y (hz) avcc = vdrive = 5v internal reference f sample = 200ksps t a = 25c 10v range all 8 channels 08096-023 figure 20 . snr vs. input frequency 10 v ra nge www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 16 of 32 0.25 ?40 ?25 ?10 5 20 35 50 65 80 ?0.25 ?0.20 ?0.15 ?0.10 ?0.05 0 0.05 0.10 0.15 0.20 bipolar zero code error (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08096- 1 19 figure 21 . bipolar zero code error vs. temperature 1.00 0.75 0.50 0.25 0 ?0.25 ?0.50 ?0.75 ?40 ?25 ?10 5 20 35 50 65 80 ?1.00 bipolar zero code error matching (lsb) temperature (c) 200ksps av cc , v drive = 5v external reference 5v range 10v range 08096-120 figure 22 . bipolar zero code error matching vs. temperature ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 1k 100k 10k ?120 thd (db) input frequency (hz) 10v range av cc , v drive = +5v f sample = 200ksps r source matched on vx and vxgnd inputs 105k? 48.7k? 23.7k? 10k? 5k? 1.2k? 100? 51? 0? 08096-121 figure 23 . thd vs . input frequency for various source impedances, 10 v range 1k 100k 10k thd (db) input frequency (hz) 5v range av cc , v drive = +5v f sample = 200ksps r source matched on vx and vxgnd inputs 105k? 48.7k? 23.7k? 10k? 5k? 1.2k? 100? 51? 0? ?40 ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 08096-122 figure 24 . thd vs. input frequency for various source impedances, 5 v range 2.5010 2.5005 2.5000 2.4995 2.4990 2.4985 ?40 ?25 ?10 5 20 35 50 65 80 2.4980 refout voltage (v) temperature (c) av cc = 4.75v av cc = 5v av cc = 5.25v 08096-125 figure 25 . reference output voltage vs. temperature for different supply voltages 8 ?10 ?8 ?6 ?4 ?2 10 8 6 4 2 0 ?10 ?8 ?6 ?4 ?2 0 2 4 6 input current (a) input voltage (v) ?40c +25c +85c av cc , v drive = 5v f sample = 200ksps 08096-126 figu re 26 . analog input current vs. i nput voltage for various temperatures www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 17 of 32 22 20 18 16 14 12 10 8 av cc supply current (ma) oversampling ratio av cc , v drive = 5v t a = 25c internal reference f sample varies with os rate no os os2 os4 os8 os16 os32 os64 08096-127 figure 27 . supply current vs. oversampling rate 140 0 1100 1000 900 800 700 600 500 400 300 200 100 60 70 80 90 100 110 120 130 power supply rejection ratio (db) av cc noise frequency (khz) av cc , v drive = 5v internal reference AD7607 recommended decoupling used f sample = 200ksps t a = 25c 10v range 5v range 08096-128 figure 28 . psrr ?50 ?60 ?70 ?80 ?90 ?100 ?110 ?120 ?130 0 160 140 120 100 80 60 40 20 ?140 channel-to-channel isolation (db) noise frequency (khz) 10v range 5v range av cc , v drive = 5v internal reference AD7607 recommended decoupling used f sample = 150ksps t a = 25c interferer on all unselected channels 08096-129 figure 29 . channel - to - channel isolation www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 18 of 32 terminology integral nonlinearity the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a t ? lsb below the first co de transition ; and full scale , at ? lsb above the last code transition. differential nonlinearity the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. bipolar zero code error the deviation of the midsca le transition (a ll 1s to all 0s) from the ideal, which is 0 v C ? lsb . bipolar zero code error match the absolute difference in bipolar zero code error between any two input channels. positive full - scale error the deviation of the actual last code transi tion from the ideal last code transition (10 v ? 1? lsb (9.99 8 ) and 5 v ? 1? lsb (4.999 08 )) after bipolar zero code error is adjusted out. the positive full - scale error includes the contribution from the internal reference buffer. positive full - scale error match the absolute difference in positive full - scale error between any two input channels. negative full - scale error the deviation of the first code transition from the ideal first code transition ( ? 10 v + ? lsb ( ? 9.99 93 ) and ? 5 v + ? lsb ( ? 4.999 69 )) afte r the bipolar zero code error is adjusted out. the negative full - scale error includes the contribution from the internal reference buffer. negative full - scale error match the absolute difference in negative full - scale error between any two input channels. signal -to - (noise + distortion) ratio the measured ratio of signal - to - (noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum o f all nonfundamental signals up to half the sampling frequency ( f s /2, excluding dc). the ratio depends on the numbe r of quantization levels in the digitization process: the more levels, the smaller the quantization noise. the theoretical signal - to - (noise + distortion) ratio for an ideal n - bit converter with a sine wave in put is given by signal - to - ( noise + distortio n ) = (6.02 n + 1.76) db th us, for a 14- bit converter, the signal - to - (noise + distortion) is 86.04 db. total harmonic distortion (thd) the ratio of the rms sum of the harmonics to the fundamental. for the ad760 7, it is defined as thd (db) = 20log 1 6 5 4 3 2 v v v v v v v v v 2 9 2 8 2 7 2 2 2 2 2 + + + + + + + where: v 1 is the rms amplitude of the fundamental. v 2 to v 9 are the rms amplitudes of the second through nin th harmonics. peak harmonic or spurious noise the ratio of the rms value of the next lar gest component in the adc output spectrum (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the no ise floor, it is determined by a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlinearities create distortion products at sum and difference frequencies of mfa nfb, whe re m , n = 0, 1, 2, 3. intermodulation distortion terms are those for which neither m nor n is equal to 0. for example, the second - order terms include (fa + fb) and (fa ? fb), and the third - order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ? 2fb). the calculation of the intermodulation distortion is per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fundamentals expressed in decibels (db) . power supply rejection ratio (psr r ) variations in power supply affect the full - scale transition but not the l inearity of the c onverter . psr is the maximum change in full - scale transition point due to a change in power supply voltage from the nominal value. the psr ratio (psrr) is defined as the ratio of the power in the adc output at full - scale frequency, f, to t he power of a 200 mv p - p sine wave applied to the adcs v dd and v ss supplies of frequency , f s . psrr (db) = 10 log ( pf / pf s ) where: pf is equal to the power at fr equency f in the adc output. pf s is equal to the power at f requency f s coupled onto the a v cc sup plies. channel -to - channel isolation channel - to - channel isolation is a measure of the level of crosstalk between any two channels. it is me asured by applying a full - scale sine wave signal of up to 160 khz to all unselected input channels , and then determini ng the degree to which the signal attenuates in the selected channel with a 1 khz sine wave signal applied (see figure 29) . www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 19 of 32 theory of operation converter details the AD7607 is a data acquisition system that empl oy s a high speed, low power, charge redistribution , successive approxi - mation analog - to - digital converter (adc) and allow s the simultaneous sampling of eight analog input channels. the analog inputs on the AD7607 can accept true bipolar input signals. the range pin is used to select either 10 v or 5 v as the input range. the AD7607 operate s from a single 5 v supply. the AD7607 contain s input clamp protection, in put signal scaling amplifiers, a second - order anti aliasing filter, track - and - hold amplifiers, a n on - chip reference, reference buffers, a high s peed adc , a digital filter , and high speed parallel and serial interfaces. sampling on the AD7607 is controlled using the convst signals. analog input analog input ranges the AD7607 can handle true bipolar in put voltages. the logic level on the range pin determines the analog input range of all analog input channels. if this pin is tied to a logic high, the analog input range is 10 v for all c hannels. if this pin is tied to a logic low, the analog input range is 5 v for all channels. a logic change on this pin has an imme diate effect on the analog input range; however , there is a typical settling time of ~ 80 s , in addition to the normal acquisition time requirement. recommended p ractice is to hardwire the ra nge pin according to the desired input range for the system signals. during normal operation, the applied analog input voltage should remain within the analog input range selected via the range pin. a reset pulse must be applied after power - up to ensure t he analog input channels are configured for the range selected. when in a power - down mode, it is recommended to tie the analog inputs to gnd. as per the input clamp protection section , the overvoltage clamp protection is recomm ended for use in transient o ver voltage conditions and should not remain active for extended periods. stressing the analog inputs outside of the conditions mentioned here may degrade the bipolar zero code error and thd performance of the AD7607. analog input impedance the analog input impedance o f the AD7607 is 1 m?. this is a fixed input impedance that does not vary with the AD7607 sampling frequency. this high analog input impedance elimi - nates the need for a driver amplifier in front of the AD7607 , allowing for direct connection to the source or sensor. w i th the need for a driver amplifier eliminated, bipolar supplies ( which are often a source of noise in a system ) can be removed from the signal chain . analog input clamp protection figure 30 shows the analog input structure of the AD7607 . each AD7607 analog input contains clamp protection circuitry. despite single 5 v supply operation , this analog input clamp prot ection allows for an input over voltage of up to 16.5 v . 08096-032 1m? clamp vx 1m? clamp vxgnd second- order lpf r fb r fb figure 30 . analog input circuitry figure 31 shows the voltage vs . current characteristic of the clamp circuit. for input voltages of up to 16.5 v , no curre nt flows in the clamp circuit. for input voltages that are above 16.5 v , the AD7607 clamp circuitry turn s on and clamp s the analog input to 16.5 v. 30 ?50 ?40 ?30 ?20 ?10 0 10 20 ?20 ?15 ?10 ?5 0 5 10 15 20 input clamp current (ma) source voltage (v) 08096-051 av cc , v drive = 5v t a = 25c figure 31 . input protection clamp p rofile a series resisto r should be placed on the analog input channels to limit the current to 10 ma for input voltages above 16.5 v. in an applicatio n where there is a series resistance on an analog input channel, vx, a corresponding resistance is required on the analog input gnd channel , vxgnd (see figure 32 ). if t here is no corresponding resisto r on the vxgnd channel, a n off set error occurs on that channel. 1m? clamp vinx 1m? clamp vxgnd r fb r fb c r r analog input signal AD7607 08096-032 figure 32 . input resistance matching on the analog i nput www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 20 of 32 analog input antia liasing filter an analog ant i alias ing filter (a second - order butterworth) is also provided on the AD7607 . figure 33 and figure 34 show the frequency and phase response , respectively , of the analog anti alias ing filter. in the 5 v range, the ? 3 db frequency is typically 15 khz. in the 10 v range , the ? 3 db frequency is ty pically 2 3 khz. 5 0 ?5 ?10 ?15 ?20 ?25 ?30 ?35 ?40 100 1k 10k 100k attenuation (db) input frequency (hz) 08096-053 10v range 5v range av cc , v drive = 5v f sample = 200ksps t a = 25c 10v range 0.1db 3db ?40 10,303 24,365hz +25 9619 23,389hz +85 9326 22,607hz 5v range 0.1db 3db ?40 5225 16,162hz +25 5225 15,478hz +85 4932 14,990hz figure 33 . analog antia lias ing filter frequency response 18 16 14 12 10 8 6 4 2 0 ?2 ?4 ?6 10 100k 10k 1k ?8 phase delay (s) input frequency (hz) 08096-052 av cc , v drive = 5v f sample = 200ksps t a = 25c 5v range 10v range figure 34 . analog antia lias ing filter phase response track - and - hold amplifiers the track - and - hold amplifiers on the AD7607 let the adc accurately acquire an input sine wave of full - scale amplitude to 14- bit resolution. the track - and - hold amplifiers sample their respective inputs simultaneously on the rising edge of convst x. the aperture time for the track - and - hold (that is, the d elay time between the external convst x signal and the track - and - hold actually going into hold ) is well matched , by design, across all eight track - and - holds on one device and from device to device. this matching allows more than one AD7607 device to be sam pled simultaneously in a system. the end of the conversion process across all eight channels is indica ted by the falling edge of busy, and it is at this point that the track - and - holds return to track mode and the acquisition time for the next set of conv ersions begins. the conversion clock for the part is internally generated, and the conversion time for all channels is 4 s . on the ad760 7 , the busy signal returns low after all eight conversions to indicate the end of the conversion process. on the fallin g edge of busy, the track - and - hold amplifiers return to track mode. new data can be read from the output register via the parallel, parallel byte , or serial interface after busy goes low ; or , alternatively , data from the previous conversion can be read whi le busy is high. reading data from the AD7607 while a conversion is in progress has little e ffect on performance and allow s a faster throughput to be achieved. in parallel mode at v drive > 3.3 v, the snr is reduced by ~1.5 db when reading during a conversi on. adc transfer functio n the output coding of the AD7607 is twos complement. the designed code transitions occur midway between successive integer lsb values, that is, 1/2 lsb, 3/2 lsb. the lsb size is fsr/16,384 . the ideal transfer characteristic is show n in figure 35. 011...111 011...110 000...001 000...000 111...111 100...010 100...001 100...000 ?fs + 1/2lsb 0v ? 1lsb +fs ? 3/2lsb adc code analog input +fs midscale ?fs lsb 10v range +10v 0v ?10v 1.22mv 5v range +5v 0v ?5v 610v +fs ? (?fs) 2 14 lsb = vin 5v ref 2.5v 5v code = 8192 vin 10v ref 2.5v 10v code = 8182 08096-035 figure 35 . transfer characteristic s the lsb size is dependent on the analog input range selected . www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 21 of 32 internal/external reference the AD7607 contains an on-chip 2.5 v bandgap reference. the refin/refout pin allows access to the 2.5 v reference that generates the on-chip 4.5 v reference internally, or it allows an external reference of 2.5 v to be applied to the AD7607. an externally applied reference of 2.5 v is also gained up to 4.5 v, using the internal buffer. this 4.5 v buffered reference is the reference used by the sar adc. the ref select pin is a logic input pin that allows the user to select between the internal reference or an external reference. if this pin is set to logic high, the internal reference is selected and enabled. if this pin is set to logic low, the internal reference is disabled and an external reference voltage must be applied to the refin/refout pin. the internal reference buffer is always enabled. after a reset, the AD7607 operates in the reference mode selected by the ref select pin. decoupling is required on the refin/refout pin for both the internal and external reference options. a 10 f ceramic capacitor is required on the refin/refout pin. the AD7607 contains a reference buffer configured to gain the ref voltage up to ~4.5 v, as shown in figure 36. the refcapa and refcapb pins must be shorted together externally, and a ceramic capacitor of 10 f applied to refgnd, to ensure that the reference buffer is in closed-loop operation. the reference voltage available at the refin/refout pin is 2.5 v. when the AD7607 is configured in external reference mode, the refin/refout pin is a high input impedance pin. for applications using multiple AD7607 devices, the following configurations are recommended, depending on the application requirements. external reference mode one adr421 external reference can be used to drive the refin/refout pins of all AD7607 devices (see figure 37). in this configuration, each refin/refout pin of the AD7607 should be decoupled with a 100 nf decoupling capacitor. internal reference mode one AD7607 device, configured to operate in the internal reference mode, can be used to drive the remaining AD7607 devices, which are configured to operate in external reference mode (see figure 38). the refin/refout pin of the AD7607, configured in internal reference mode, should be decoupled using a 10 f ceramic decoupling capacitor. the other AD7607 devices, configured in external reference mode, should use a 100 nf decoupling capacitor on their refin/refout pins. buf sar 2.5v ref refcapb refin/refout refcapb 10f 0 8096-036 figure 36. reference circuitry AD7607 ref select refin/refout AD7607 ref select refin/refout 100nf 0.1f 100nf AD7607 ref select refin/refout 100nf adr421 08096-038 figure 37. single external reference driving multiple AD7607 refin pins AD7607 ref select refin/refout + 10f AD7607 ref select refin/refout 100nf AD7607 ref select refin/refout 100nf v drive 08096-037 figure 38. internal reference driving multiple AD7607 refin pins. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 22 of 32 typical connection d iagram figure 39 sh ows the typical connection diagram for the AD7607 . there are four avcc supply pins on the part, and each of the four pins should be decoupled using a 100 nf cap acitor at each supply pin and a 10 f capacitor at the supply source. the AD7607 can operate wit h the internal reference or an externally applied reference. in this configuration, the AD7607 is configured to operate with the internal reference. when using a single AD7607 device on the board , the refin/refout pin should be decoupled with a 10 f capac itor . when using an application with multiple AD7607 devices , refer to the internal/external reference section . t he refcap a and refcapb pins are shorted together and decoupled with a 10 f ceramic capacitor. the v drive supply is c onnected to the same supply as the processor. the v drive voltage controls the voltage value of the output logic signals. for layout, decoupling , and grounding hints , see the layout guidelines section. power - down modes t wo power - do wn modes are available on the AD7607 : standby mode and shutdown mode. the stby pin controls whether the AD7607 is in normal mode or in one of the two power - down modes. the power - down mode is selected through the state of the range pin wh en the stby pin is low. table 7 s hows the configurations required to choo se the desired power - down mode. when the AD7607 is placed in standby mode, current consumption is 8 ma max imum and power - up t ime is approxi mately 100 s because the capacitor on the refcapa and r efcapb pins must charge up. in s tandby mode , the on - chip reference and regulators remain powered up , and the amplifiers and adc core are powered down. when the AD7607 is placed in s hutdown mode , curr ent consumption is 6 a max imum and power - up time is approximately 1 3 ms (external reference mode) . in s hutdown mode , all circuitry is powered down. when the AD7607 is powered up from shutdown mode, a reset signal must be applied to the AD7607 after the re quired power - up time has elapsed. table 7 . power -d own mode selection power - down m ode stby range standby 0 1 shutdown 0 0 av cc agnd v drive + refin/refout db0 to db15 convst a, convst b cs rd busy reset AD7607 1f 10f 100nf digital supply voltage +2.3v to +5v analog supply voltage 5v 1 eight analog inputs v1 to v8 parallel interface 1 decoupling shown on the av cc pin applies to each av cc pin (pin 1, pin 37, pin 38, pin 48). decoupling capacitor can be shared between av cc pin 37 and pin 38. 2 decoupling shown on the regcap pin applies to each regcap pin (pin 36, pin 39). regcap 2 + 10f refcapa refcapb os 2 os 1 os 0 oversampling 100nf v1 par/ser sel stby ref select range v2 v3 v4 v5 v6 v7 v8 refgnd v1gnd v2gnd v3gnd v4gnd v5gnd v6gnd v7gnd v8gnd v drive v drive microprocessor/ microconverter/ dsp 08096-039 figure 39 . typical connection diagram www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 23 of 32 conversion control si multaneous sampling on all analog input channels the AD7607 allow s simultaneous sampling of all analog input channels. all channels are sampled simultaneously when both convst pins ( convst a, convst b ) are tied togeth er. a single convst signal is used to c ontrol both convst x inputs . the rising edge of this common convst signal initiates simultaneous sampling on all analog input channels. the AD7607 contains an on - chip oscillator that is used to perform the conversions. the conversion time for all adc chann els is t conv . the busy signal indicates to the user when conversions are in progress, so when the rising edge of convst is applied, busy goes logic high and transitions low at the end of the entire conversion process. the falling edge of the busy signal is used to place all eight track - and - hold amplifiers back into track mode. the falling edge of busy also indicates that the new data can now be read from the parallel bus (db[15:0]), the d out a and d out b serial data lines, or the parallel byte bus ( db[7:0] ) . simultaneously sampling two sets of c hannels the AD7607 also allow s the analog input channels to be sampled simultaneously in two sets. this can be used in power - l ine protection and measurement systems to compensate for phase difference s between current an d voltage sensors . in a 50 hz syste m, this allows for up to 9 of phase compensation; and in a 60 hz system, it allows for up to 10 of phase compensation. this is accomplished by pulsing the two convst pins independently and is possible only if oversam pling is not in use. convst a is used to initiate simultaneous sampling of the first set of channels (v1 to v 4), and convst b is used to initiate simultaneous sampling on the seco nd set of analog input channels ( v 5 to v 8) , as illustrated in figure 40. on the rising edge of convst a , the track - and - hold amplifiers for the first set of channels are placed into hold mode . on the rising edge of convst b , the track - and - hold amplifiers for the second set of channels are placed into hol d mode . the conversion process begins when both rising edges of convst x have occurred; therefore , busy goes high on the rising edge of the later convst x signal. in table 3 , time t 5 indicates the maximum allowable time between co nvst x sampling points. there is no change to the data read process when using two separate convst x signals. connect all unused analog input channels to agnd. the results for any unused channels are still included in the data read because all channels are always converted. convst a convst b busy cs/rd data: db[15:0] frstdata v1 v2 v3 v7 v8 t 5 t conv v1 to v4 track-and-hold enter hold v5 to v8 track-and-hold enter hold AD7607 converts on all 8 channels 08096-040 figure 40 . simultaneous sampling on channel sets while using i ndependent convst a and convst b signals parallel interface m ode www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 24 of 32 digital interface the AD7607 provide s three interface options: a parallel in ter - face , a high speed serial interface , and a parallel byte interface . the required interface mode is selected via the pa r /ser /byte sel and the db15 /byte sel pin s. table 8 . interface mode s election par /ser /byte sel db15 interface mode 0 0 parallel interfac e mode 1 0 serial interface mode 1 1 parallel byte interface mode interface mode operation is discussed in the following sections. parallel interface ( par /ser/byte sel = 0) data can be read from the AD7607 via the parallel data bus with standard cs and rd signals. to read the data over the parallel bus, the pa r /ser/byte sel pin should be tied low. the cs and rd input signals are internally gated to enable the conversion result onto the data bus. the data lines , db15 to db0 , leave their high impedance state when both cs and rd are logic low. when cs and rd are low, db15 and db14 are used to output a sign extended bit of the msb (db13) of the conversion result. AD7607 14 busy 12 rd 33:16 db[15:0] 13 cs digital host interrupt 08096-041 figure 41 . interface diagram one AD7607 using the parallel bus, with cs and rd shorted together the rising edge of the cs input signal tri states the bus , and the falling edge of the cs input signal takes the bus out of the high impedance state. cs i s the control sig nal that enables the data lines; it is the function that allows multiple AD7607 devices to share the same parallel data bus. the cs signal can be permanently tied low, and the rd signal can be used to a ccess the conversion results as shown in figure 4 . a read operation of new data can take place after the busy signal goes low ( see figure 2 ); or , alternatively , a read operation of data fr om the previous conversion process can take place while busy is high ( see figure 3 ) . the rd pin is used to read data from the output conversion results register. applying a sequence of rd pulses to the rd pin of the AD7607 clocks the conversion results out from each channel onto the parallel output b us , db[15:0] , in ascending order. the first rd falling edge after busy goes low clocks out the conversion result from c hannel v1 . t he next rd falling edge updates the bus with the v2 conversion result , and so on. t he eighth falling edge of rd clocks out the conversion result for c hannel v8. when the rd signal is l ogic low, it enables the data conversion result from each channel to be transferred to the digital host (dsp, fpga). when there is only one AD7607 in a system/ board and it does not share the parallel bus, data can be read using just one control signal from the digital host. the cs and rd signals can be tied together , as shown in figure 5 . in this case , the data bus comes out of three - state on the falling edge of cs / rd . the combined cs and rd signal allows the data to be clocked out of the AD7607 and to be read by the digital host. in this case , cs is used to frame the data transfer of each dat a channel. parallel byte interf ace ( par /ser/byte sel = 1, db15 = 1) parallel byte interface mode operates much like the parallel interface mode, except that each channel conversion result is read out in two 8 - bit transfers. therefore, 16 rd pulses are required to read all eight conversion results from the AD7607. to configure the AD7607 to operate in parallel byte interface mode, the par /ser/ byte sel and byte sel/db15 pins should be tied to logic high ( see table 8 ). db[7:0] are used to transfer the data to the digital host. db0 is the lsb of the data transfer, and db7 is the msb of the data transfer. in parallel byte mode, db14 acts as an hben pin. when the db14/ hben pin is tied to logic high, the most significant byte (msb) of the conversion result is output first, followed by the lsb byte of the conversion result. when db14 / hben is tied to logic low, the lsb byte of the conversion result is output first, followe d by the msb byte of the conversion result. the frstdata pin remains high until the entire 14 bits of the conversion result from v1 is read. if the msb byte is always to be read first, the hben pin should be set high and remain high. if the lsb byte is alw ays to be read first, the hben pin should be set low and remain low. in this circumstance, the msb byte contain s two sign extended bits in the two msb positions. serial inte rface ( par /ser /byte sel = 1) to read data back from the AD7607 o ver the serial interface, the pa r /ser/byte sel pin must be tied high. the cs and sclk signals are used to transfer data from the AD7607 . the AD7607 has two serial data output pins, d out a and d out b. data can be read back from the AD7607 using one or both of these d out lines. for the AD7607 , conversion results from channel v1 to channel v4 first appear on d out a , and conversion results from channel v5 to channel v8 first appear on d out b. the cs falling edg e takes the data output lines , d out a and d out b, out of three - state and clocks out the msb of the conversion result. the rising edge of sclk clocks all subsequent data bits onto the serial data outputs , d out a and d out b. the cs input can be held low for the entire serial read , or it can be pulsed to frame each chan nel read of 14 sclk cycles. www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 25 of 32 figure 42 shows a read of eight simultaneous conversion results using two d out lines on the AD7607 . in this case , a 56 sclk transfer is used to access data from the AD7607 , and cs is held low to frame the entire 56 sclk cycles. data can also be clocked out using just one d out line; in which case , it is recom mended that d out a be use d to access all conversion da ta because the channel data is output in ascending order. for the AD7607 to access all eight conversion results on one d out line , a total of 1 12 sclk cycles are required. these 112 sclk cycles can be framed by one cs signal , or each group of 14 sclk cycles can be individually framed by the cs signal. the disadvantage of using just one d out line is that the throughput rate is reduced if reading occurs after conversion. the unused d out line should be l eft unconnected in se rial mode. i f d out b is to be used as a single d out line, the channel results are output in the following order : v5, v6, v7, v8, v1, v2, v3, and v4; however , the frstdata indicator return s low after v5 is read on d out b. figure 6 s hows the timing diagram for reading one channel of data, framed by the cs signal, from the AD7607 in serial mode. the sclk input signal provides the clock source for the serial read operation. the cs goes low to access t he data from the AD7607 . the falling edge of cs takes the bus out of three - state and clocks out the msb of the 14 - bit conversion result. this msb is valid on the first falling edge of the sclk after the cs falling edge. the subsequent 13 data bits are clocked out of the AD7607 on the sclk rising edge. data is valid on the sclk falling edge. to a ccess each conversion result , 14 clock cycles must be provided . the frstdata output signal indicates when the first channel, v1, is being read back. when the cs input is high, the frstdata output pin is in three - state. in serial mode, the falling edge of cs takes frstdata out of three - state and set s the frstdata pin high, indicating that the resu lt from v1 is available on the d out a output data line . t he frstdata output returns to a logic low following the 14 th sclk falling edge. if all channels are read on d out b, the frstdata output does not go high when v1 is output on this serial data output pin . it goes high only when v1 is available on d out a (and this is when v5 is available on d out b ) . reading during conve rsion data can be read from the AD7607 while busy is high and the conversions are in progress. this has little e ffect the performance of the converter , and it allows a faster throughput rate to be achieved. a parallel, parallel byte, or serial read can be performed d uring conversions and when over sampling is or is not enabled . figure 3 shows the timing diagram for read ing while busy is high in parallel or serial mode. reading during conversions allows the full throughput rate to be achieved when using the serial interface with v drive above 3.3 v . data can be read from the AD7607 at any time other than on the falling edg e of busy because this is when the output data registers get updated with the new conversion data. time t 6 , as outlined in table 3 , should be observed in this condition. v1 v4 v2 v3 v5 v8 v6 v7 sclk d out a d out b cs 56 08096-042 figure 42 . serial interface wit h t wo d out lines www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 26 of 32 digital f ilter the AD7607 contain s an optional first - order digital sinc filter that should be used in applications where slower throughput rates are used and digital filtering is required . the oversampling ratio of the digital filter is controlled using the ov ersampling pins , os[2:0] ( see table 9 ) . os 2 is the msb control bit , and os 0 is the lsb control bit. table 9 list s th e over sampling bit decodi ng to select the different over sample rates. the os pins are latched on the falling edge of busy. this set s the over sampli ng rate for the next conversion ( see figure 43) . selection of the oversampling mode has the effect of adding a d igital filter function after the adc. the different oversampling rates and the convst x sampling frequency produce different digital filter frequency profiles. table 9 . overs ample bit decoding os [2:0] oversampling ratio 3 db bw, 5 v range (khz) 3 db bw, 10 v range (khz) maximum throughput , convst f requency (khz) 000 no oversampling 15 22 200 001 2 15 22 100 010 4 13.7 18.5 50 011 8 10.3 11.9 25 100 16 6 6 12.5 101 32 3 3 6.25 110 64 1.5 1.5 3.125 111 invalid convst a and convst b busy os x t os_setup t os_hold conversion n conversion n + 1 oversample rate latched for conversion n + 1 08096-043 figur e 43 . os x pin timing www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 27 of 32 figure 44 to figure 49 show the digital filter frequency profiles for the different over sampling ratios. the com bination of the analog antialiasing filter and the oversampling digital filter help s to reduce the complexity of the design of the filter before the AD7607. the digital filtering combines steep roll - off and linear phase response. ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m a ttenu a tion (db) frequenc y (hz) av cc = v drive = 5v t a = 25c 10v range os by 2 08096-0 1 1 figure 44 . digital filter response for ove rsampling by 2 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m a ttenu a tion (db) frequenc y (hz) av cc = v drive = 5v t a = 25c 10v range os by 4 08096-012 figure 45 . digital f i lter response for oversampling by 4 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m a ttenu a tion (db) frequenc y (hz) av cc = v drive = 5v t a = 25c 10v range os by 8 08096-013 figure 46 . digital filter response for oversampling by 8 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m a ttenu a tion (db) frequenc y (hz) av cc = v drive = 5v t a = 25c 10v range os by 16 08096-014 figure 47 . digital filter response for overs ampling by 16 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m a ttenu a tion (db) frequenc y (hz) av cc = v drive = 5v t a = 25c 10v range os by 32 08096-015 figure 48 . digital filter response for oversampling by 32 ?90 ?80 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 100 1k 10k 100k 1m 10m a ttenu a tion (db) frequenc y (hz) av cc = v drive = 5v t a = 25c 10v range os by 64 08096-016 figure 49 . digital filter response for oversampling by 64 www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 28 of 32 ?2 ?1 0 code number of occurances 1 2 2000 1800 1600 1400 1200 1000 800 600 400 200 0 av cc = 5v v drive = 5v t a = 25c 10v range os64 08096-130 figure 50 . histogram of codes , o versamplin g by 64 if the os [2:0] pins are set to select an oversampling ratio of 8, for example, the next convst x rising edge takes the first sample for each channel . t he remaining seven samples for all channels are taken with an internally generated sampling signa l. as the oversampling ratio is increased, the 3 db frequency is reduced and the allowed sampling frequency is also reduced (see table 9 ). the os[2:0] pins should be configured to suit the filtering requirements of the application. the convst a and convst b pins must be tied/driven together when oversampling is turned on. when the oversampling function is turned on, the busy high time for the conversion process extends. the actual busy high time depends on the ove r - sampling rate that is selected: the higher the oversampling rate, the longer the busy high or total conversion time (see table 3 ) . figure 51 shows that the conversion time extends as the over - sampling r ate is increased. to achi eve the fastest throughput rate possible when oversampling is turned on, the read can be per formed during the busy high time. the falling edge of busy is used to update the output data registers with the new conversion data ; theref ore, the reading of conversion data should not occur on this edge. cs rd data: db[15:0] busy convst a and convst b t cycle t conv 4s t 4 t 4 t 4 19s 39s os = 0 os = 4 os = 8 08096-044 figure 51 . no oversampling, overs amp l ing by 4, and overs ampling by 8 using read after conversion www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 29 of 32 layout g uidelines the printed circuit board that houses the ad76 07 should be designed so that the analog and digital sections are separated and confined t o different areas of the board. at least one ground plane should be used. it can be common or split between the digital and analog sections. in the case of the split plane, the digital and analog ground planes should be joined in only one place, preferably as close as possible to the AD7607 . if the AD7607 is in a system where multiple devices require analog - to - digital ground connections, the connection should still be made at only one p oint: a star ground point that should be established as close as possible to the AD7607 . good connections should be made to the ground plane. avoid sharing one connecti on for multiple ground pins. use i ndividual vias or multiple vias to the ground plane for each ground pin. avoid running digital lines under the devices because doing so couples noise onto the die. the analog ground plane should be allowed to run under the AD7607 to avoid noise coupling. fast switching signals like convst a, convst b , or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and they should never run near analog signal paths. avoid c rossover of digital and analog signals. traces on layers in close proximity on the board should run at right angles to each other to reduce the effect of feedthrough through the board. the power supply lines to the av cc and v drive pins should use as large a trace as possible to provide low impedance paths and reduce the effect of gl itches on the power supply lines. where possible , use supply planes and make good connections between the AD7607 supply pins an d the power tracks on the board . u se a single via or multiple vias for each supply pin. good decou pling is also important in lowering the supply impedance presented t o the AD7607 and in reducing the magnitude of the supply spikes. the decoupling capaci tors should be placed close to ( ideally , righ t up against) these pins and their corresponding ground p ins. place t he decoupling capacitors for the refin/refout pin and the refcapa an d refcapb pins as close as possible to their respe ctive AD7607 pins ; and , where possible , they should be placed o n the same side of the board as the AD7607 device. figure 52 shows the recommended decoupling on the top layer of the AD7607 board. figure 53 shows bottom layer decoupling, which is used for the four av cc pins and the v drive pin. 08096-048 figure 52 . top layer decoupling refin/refout, refcapa, refcapb , and regcap p ins 08096-049 figure 53 . bottom layer d ecoupling www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 30 of 32 to ensure good device - to - device performance matching i n a system that contains multiple AD7607 devices, a symmetrical lay out between the devices is important. figure 54 shows a layout wi th two AD7607 devices. the av cc supply plane runs to the right of both devices. the v drive supply track runs to the left of the two AD7607 devices. the reference chip is positioned between the two AD7607 devices , and the referen ce voltage track runs north to pin 42 of u1 and south to pin 42 of u2. a solid ground plane is used. these symmetrical layout principles can also be applied to a s ystem that co ntains more than two AD7607 devices. the AD7607 dev ices can be placed in a north - s outh direction with the reference voltage located midway between the AD7607 devices and the refer ence track running in the north - south direction , similar to figure 54. avcc u2 u1 avcc u2 u1 08096-050 figure 54 . layout for multiple AD7607 devices top layer and supply plane layer www.datasheet.co.kr datasheet pdf - http://www..net/
data sheet AD7607 rev. b | page 31 of 32 outline d imensions compliant t o jedec s t andards ms-026-bcd 051706- a t op view (pins down) 1 16 17 33 32 48 49 64 0.27 0.22 0.17 0.50 bsc lead pitch 12.20 12.00 sq 1 1.80 pin 1 1.60 max 0.75 0.60 0.45 10.20 10.00 sq 9.80 view a 0.20 0.09 1.45 1.40 1.35 0.08 coplanarit y view a ro ta ted 90 ccw se a ting plane 0.15 0.05 7 3.5 0 figure 55 . 64 - lead low profile quad flat package [lqfp] (st - 64 - 2) dimensions shown in millimeters ordering guide model 1 temperature range package description package option AD7607 bstz ? 40c to +85c 64- lead low profile quad flat package [lqfp] st -64- 2 AD7607 bstz - rl ? 40c to +85c 64- lead low profile quad flat pa ckage [lqfp] st -64- 2 eval - AD7607edz ? 40c to +85c evaluation board ced1z converter evaluation development 1 z = rohs compliant part. www.datasheet.co.kr datasheet pdf - http://www..net/
AD7607 data sheet rev. b | page 32 of 32 notes ? 2010 - 2012 analog devices, inc. all rights reserved. trademarks and registered trade marks are the property of their respective owners. d08096 - 0- 1/12(b) www.datasheet.co.kr datasheet pdf - http://www..net/

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